Through Silicon via Bridge Interconnect

ABSTRACT

An integrated circuit bridge interconnect device includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The bridge die includes through silicon vias (TSVs) to connect conductive interconnect lines on the bridge die to the first die and the second die. Active circuitry, other than interconnect lines, may be provided on the bridge die. At least one or more additional die may be stacked on the bridge die and interconnected to the bridge die.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of co-pending U.S. patent applicationSer. No. 12/164,331 filed Jun. 30, 2008, entitled “THROUGH SILICON VIABRIDGE INTERCONNECT”.

TECHNICAL FIELD

This disclosure relates to integrated circuit (IC) packaging, and morespecifically to bridge interconnections between side-by-side integratedcircuits within a substrate package.

BACKGROUND

In IC packaging there is a need to provide semiconductor dies in aside-by-side configuration within a package and interconnect them. Thepackage may be, for example, a lead frame package.

In one configuration, semiconductor dies are packaged with the activeside of each die facing away from the package base. Interconnectionbetween dies is achieved by wire bonding. However, design rules forassembly interconnection may be limited by dimensions of the wirediameter and wire-bonding capillary tool, requiring bonding pads thatare large enough and spaced sufficiently far apart to accommodate thedimensions. Thus the number of interconnects is limited by the size ofthe interconnects. In addition, lead inductance in the die-to-die wirebond may limit performance of the packaged device. Furthermore, goldwire is a conventional choice for wire bonding, increasing significantlythe net cost of the package.

In another configuration, flip-chip solderball packaging, the activedevice region of the die is on the surface facing the package mountingsubstrate, e.g., downward. In this configuration, interconnectiondensity between adjacent dies is also limited by contact pad sizerequirements.

U.S. Pat. No. 5,225,633 discloses interconnecting two semiconductor diesin a side-by-side configuration using bridge elements. Each bridgeelement comprises a rigid silicon die supporting overhanging conductingbeam leads. The bridge is placed in a space between two semiconductordies, and the extent of overhang of each beam lead and adjacentpositioning are selected to provide proper mating with bonding padspositioned on each of the semiconductor dies to be interconnected.However, no method of forming the beam leads or disposing them on thesilicon bridge is disclosed. Moreover, handling and assembling beamleads may be difficult, and the bridge occupies space between the twodies. Furthermore, as gold is a preferred interconnect metal, there isan impact on the material cost of the assembled package.

There is a need, therefore, for a packaging interconnect system betweenadjacent semiconductor dies that simplifies the assembly process,reduces the cost of interconnect materials, and enables interconnectionbetween chips with a finer pitch than is conventionally permissible withwire bonding and equivalent beam lead interconnections.

SUMMARY

A system and method to interconnect two die in a side-by-sideconfiguration is disclosed. A third semiconductor die functions as aninterconnection bridge to connect the two die. The bridge die includesthrough silicon vias (TSVs) to facilitate the interconnection.

An integrated circuit bridge interconnect system includes a first diehaving a first side and a second side and a second die having a firstside and a second side. These die are provided in a side-by-sideconfiguration. A bridge die is disposed on the first sides of the firstdie and the second die. The bridge die interconnects the first die andthe second die.

An integrated circuit packaging system includes a package to containsemiconductor dies and a substrate disposed within the package forreceiving semiconductor dies. A first die and a second die, both havinga first side and a second side, are disposed on the substrate in aside-by-side configuration. The second sides of the first and seconddies face the substrate. A bridge die is disposed on the first sides ofthe first die and the second die. The bridge die interconnects the firstdie and the second die.

The foregoing has outlined rather broadly the features and technicaladvantages of the present invention in order that the detaileddescription of the invention that follows may be better understood.Additional features and advantages of the invention will be describedhereinafter which form the subject of the claims of the invention. Itshould be appreciated by those skilled in the art that the conceptionand specific embodiment disclosed may be readily utilized as a basis formodifying or designing other structures for carrying out the samepurposes of the present invention. It should also be realized by thoseskilled in the art that such equivalent constructions do not depart fromthe spirit and scope of the invention as set forth in the appendedclaims. The novel features which are believed to be characteristic ofthe invention, both as to its organization and method of operation,together with further objects and advantages will be better understoodfrom the following description when considered in connection with theaccompanying figures. It is to be expressly understood, however, thateach of the figures is provided for the purpose of illustration anddescription only and is not intended as a definition of the limits ofthe present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, reference isnow made to the following descriptions taken in conjunction with theaccompanying drawings, in which:

FIG. 1 shows an exemplary wireless communication system in whichembodiments of the invention may be advantageously employed.

FIG. 2 illustrates a plan view of a TSV bridge interconnect according toan embodiment of the invention.

FIG. 3 is an exemplary exploded cross-section view of an embodiment ofbridge interconnect between two flip-chip dies.

FIG. 4 is an exemplary exploded cross-section view of an embodiment ofbridge interconnect between two wire-bond dies.

FIG. 5 is an exemplary exploded cross-section view of an embodiment ofbridge interconnect between a flip-chip die and a wire-bond die.

FIG. 6 is an exemplary exploded cross-section view of an embodiment inwhich additional dies are stacked on a bridge interconnect.

DETAILED DESCRIPTION

Methods and structures are disclosed for connecting two semiconductordie (chips), which are placed in a side-by-side configuration in asubstrate-based package. The connections may be accomplished by using asemiconductor interconnect bridge die (typically silicon) to makecontact with both side-by-side dies. The interconnect bridge die hasthrough silicon vias to connect contact pads on each of the dies to theopposite surface of the interconnect bridge die. Interconnect lines onthe interconnect bridge die are formed to complete the connectionsbetween the through silicon vias.

FIG. 1 shows an exemplary wireless communication system 100 in which anembodiment of the invention may be advantageously employed. For purposesof illustration, FIG. 1 shows three remote units 120, 130, and 150 andtwo base stations 140. It will be recognized that typical wirelesscommunication systems may have many more remote units and base stations.Remote units 120, 130, and 150 include through silicon via (TSV) bridgeinterconnect multi-chip packages 125A, 125B and 125C, which is anembodiment of the invention as discussed further below. FIG. 1 showsforward link signals 180 from the base stations 140 and the remote units120, 130, and 150 and reverse link signals 190 from the remote units120, 130, and 150 to base stations 140.

In FIG. 1, remote unit 120 is shown as a mobile telephone, remote unit130 is shown as a portable computer, and remote unit 150 is shown as afixed location remote unit in a wireless local loop system. For example,the remote units may be cell phones, hand-held personal communicationsystems (PCS) units, portable data units such as personal dataassistants, or fixed location data units such as meter readingequipment. Although FIG. 1 illustrates remote units according to theteachings of the invention, the invention is not limited to theseexemplary illustrated units. The invention may be suitably employed inany device which includes a multi-chip package having chips in aside-by-side configuration.

FIG. 2 illustrates a plan view of a TSV bridge interconnectconfiguration 200 according to an embodiment of the invention.Configuration 200 includes a substrate 210, which may be, for example,an organic or ceramic substrate printed circuit board. Two or more die,where each die has a first and a second side, may be placed on thesubstrate 210. For exemplary illustration, referring to FIG. 2, the twodie 220 and 230 are shown placed in a side-by-side configuration. Onesurface of the dies 220 and 230 may connect to the substrate 210, andeventually to package leads.

A bridge interconnect die 240 having a first and a second side at leastpartially overlaps and electrically communicates with the dies 220 and230. Through silicon vias (TSVs) 270 filled with conductive metal,connect the first side (shown facing out of the page) of the bridgeinterconnect die 240 to the active circuitry on the dies 220 and 230.Interconnect lines 272 on the first side of the bridge interconnect die240 then complete the connections between dies 220 and 230. Fordifferent functional applications, where the specific functions of thedies 220 and 230 change, the interconnect lines 272 may be appropriatelyre-routed and the TSVs 270 relocated by a change in photomasks andfabrication at the wafer scale level of processing.

Furthermore, while the interconnect lines 272 may principally be passivemetal interconnects, they may also be more complicated circuitryinterconnects, such as impedance components (i.e., resistors, capacitorsand inductors), and active devices (i.e., transistors, logic, memory,etc.). Although not shown in FIG. 2, the first side of the bridgeinterconnect die 240 can include additional active circuitry, unrelatedto the interconnect functionality.

The interconnect lines 272 and/or circuitry on the bridge interconnectdie 240 may be formed at the wafer level, including formation of themetal filled holes TSVs 270 using conventional semiconductor andmetallization processes, after which the wafer may then be separatedinto individual bridge interconnect dies 240.

FIG. 3 is an exemplary exploded cross-section view of an embodiment of aconfiguration 300 of a bridge interconnect between two flip-chip dies.The active circuitry of the flip-chip die 320 and die 330 is on thesecond sides, facing the substrate 210. Dies 320 and 330 may attach tothe substrate 210 by, for example, solder-ball bonding, or equivalentmethods used in packaging integrated circuits.

Through silicon vias (TSVs) 373 are formed through the thickness of thedies 320 and 330 to provide for metallic interconnection between thefirst sides (shown facing up in FIG. 2) and the active circuitry on thesecond sides of dies 320 and 330.

Contact pads 371 on the second side of the bridge interconnect die 240and the first sides of the dies 320 and 330 are aligned, and may bebonded using methods such as, for example, solder-ball bonding, andconductive paste. The contact pads 371 formed on the dies 320, 330 and240 enable conductive contact between the corresponding TSVs 270 and373. Consequently , the active circuitry on the dies 320 and 330 areelectrically connected to the first side of the bridge interconnect die240, where the interconnection between the active circuitry is completedusing interconnect lines 272. Contact pads 371 are shown interconnectingthe active circuitry and the solder balls.

FIG. 4 is an exemplary exploded cross-section view of an embodiment of aconfiguration 400 of a bridge interconnect between two wire bond dies420 and 430. The bridge interconnect die 240 may be substantially thesame as the bridge interconnect die 240 shown in FIG. 3. That is, thebridge interconnect die 240 of FIG. 4 may have the same features andarrangement of TSVs 270, contact pads 371, interconnect lines 272 andoptionally, impedance elements and/or active devices, also placed on thefirst side of the bridge interconnect die 240 of FIG. 3.

Semiconductor wire bond dies 420 and 430 both have a first side and asecond side, where the second sides of the dies 420 and 430 face and areattached to the substrate 210. Wire bonding connects contact pads on thefirst sides of the dies 420 and 430 to contact pads on the substrate210. As in the flip-chip configuration 300 of FIG. 3, all three dies420, 430 and 240 have contact pads 371 at corresponding locations toenable interconnection of circuitry of the dies 420 and 430 through thebridge interconnect die 240.

Active circuitry on the dies 420 and 430 are located on the firstsurface (i.e., facing away from the substrate 210). In configuration400, because the active circuitry is on the first side, the inclusion ofTSVs 373 in the dies 420 and 430, as shown in FIG. 4, may be optionallyincluded, or may not be required.

FIG. 5 is an exemplary exploded cross-section view of an embodiment of aconfiguration 500 of a bridge interconnect between the flip-chip die 320and the wire-bond die 430. Appropriate compensation may be made forrelative differences in die thickness, ball-bond height, etc., toposition the first sides of both dies 320 and 430 at the same height.Consideration of appropriate interfaces between flip-chip, bridge andwire-bond dies are the same as described with reference to FIGS. 3 and4. For example, the flip-chip die 320 has active circuitry disposed onthe second side (i.e., facing the substrate 210) and may require aplurality of TSVs 373 connected to contact pads 371 on the first side tofacilitate connections to the bridge interconnect die 240. The wire bonddie 430, on the other hand, has active circuitry disposed on the firstside (i.e., facing away from the substrate 210), and may not require theTSVs 373. Instead, the contact pads 371 connected to the activecircuitry may be sufficient.

FIG. 6 is an exemplary cross-section view of an embodiment of aconfiguration 600 in which at least one or more additional dies 640(where, for illustrative purposes, only one die 640 is shown) arestacked on the bridge interconnect die 240. The additional die 640 mayinclude a functionality, material technology or other basis for formingthe die 640 separately from other dies 320, 430 containing activedevices. The interconnect bridge die 240 can include contact pads 371 onthe first side to interface with corresponding contact pads 371 facingopposite and located on the die 640. The die 640 may include TSVs 674connected to contact pads 371 on both sides of the die 640 to provideinterconnection between the interconnect bridge die 240 and interconnectlines 672 and/or functional circuitry on the top surface of the die 640.Examples of functionality of the die 640 include memory, delay,amplifiers, logic, etc. Stacking of additional dies 640 over theinterconnect bridge die 240 may be considered, according tofunctionality, packaging and other desired objectives. Where ballbonding is employed to interconnect pads on (vertically stacked)adjacent die, the disposition of circuitry may be on either the first orthe second side of the die 640.

Numerous advantages may be derived from the embodiments described. Usinga bridge die, the interconnect traces may be fabricated in quantity atwafer scale using semiconductor processes. Metallization thickness maybe on the order of a few microns or less, with line widths suitable toadvancing technology nodes such as 45 nm and less. The metal may beother than gold. Compared to gold wire bonding between substrates,substantial material savings may be realized.

Additionally, wire bonding requires a minimum spacing between adjacentcontact pads on a substrate, for reasons due, at least in part, to thesize of the capillary tip used in wire bonding. In contrast, a very finepitch of the interconnect traces on the bridge die is possible, makingdense interconnects possible. Furthermore, with wire bonding, each bondis accomplished individually, whereas with a bridge interconnect,multiple bonds are accomplished with one chip-level placement andbonding methods such as, for example, solder reflow.

Furthermore, where a side-by-side multi-chip configuration has beenpreviously designed for wire bonding, a bridge interconnect may bebeneficially implemented to replace wire bonding, while making use ofexisting contact pads. A bridge interconnect replacement for wirebonding reduces the number of assembly steps from multiple separate wirebond steps to a single die placement.

Still furthermore, wire bonding typically involves a loop in the arc ofthe wire between two bonding pads in addition to a minimum requireddistance between bonding pads. As a result wire inductance may degradeperformance, especially in high speed devices where inductive impedanceincreases with frequency. Electromagnetic radiation from the leads maybe undesirably detected elsewhere on the chips within the package. Witha bridge die, the dies to be connected may be placed close together,reducing radiation and increasing package utilization efficiency. Thebridge die may be made quite small, with correspondingly shorterinterconnect paths than would be required with wire bonds.

A yet further advantage is the efficient ability to include in a singlepackage two or more integrated circuits that require differentmaterials, process flows or technology nodes to optimize the “systemlevel” performance afforded by the customized benefits of each chip.This enables higher level functionality in a single package.

A still further advantage is the ability to include functionality on thebridge die, which cannot be enabled by wire bonding alone.

Many of the same advantages apply when flip-chip bonding is used topackage integrated circuit dies. By implementing TSVs on flip-chip dies,fine pitch interconnects and economy of wire routing space may beenabled.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. For example,although a read operation has been used in the discussion, it isenvisioned that the invention equally applies to write operations.Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. For example, whereas TSV is a common term of artreferring to vias in silicon dies, vias may be formed in othermaterials, and in particular other semiconductor dies such as GaAs, SiC,GaN, or other suitable materials. The term TSV may be applied withapplication to any such materials. As one of ordinary skill in the artwill readily appreciate from the disclosure of the present invention,processes, machines, manufacture, compositions of matter, means,methods, or steps, presently existing or later to be developed thatperform substantially the same function or achieve substantially thesame result as the corresponding embodiments described herein may beutilized according to the present invention. Accordingly, the appendedclaims are intended to include within their scope such processes,machines, manufacture, compositions of matter, means, methods, or steps.

1. A bridge die, comprising: through vias; and a conductive layercoupled to the through vias, the conductive layer and the through viaselectrically coupling a first die to a second die.
 2. The die of claim1, in which the through vias extend from a first side of the bridge dieto a second side of the bridge die, the through vias being filled withconductive material to couple conductive lines on the first side of thebridge die to enable the interconnecting.
 3. The die of claim 2, furthercomprises active circuitry on the first side.
 4. The die of claim 2,further comprising at least one contact pad on the second side of thebridge die corresponding to at least one contact pad on first sides ofthe first and second die.
 5. The die of claim 2, in which at least oneof the first and second dies comprise: a flip-chip die having circuitrydisposed on a second side; and flip-chip through vias from a first sideof the flip-chip die to the second side of the flip-chip die, theflip-chip through vias being filled with conductive material to coupleactive circuitry on the second side of the flip-chip die to at least onecontact pad on the first side of the flip-chip die.
 6. The die of claim2, in which at least one of the first and second dies comprisescircuitry disposed on a first side of the first and second die.
 7. Thedie of claim 2, further comprising: contacts operable to couple to atleast one additional die stacked on the bridge die, the at least oneadditional die further comprising at least one of passive, active andinterconnect circuitry.
 8. The die of claim 1, fabricated using aprocess flow that is different from a process flow corresponding to atleast one of the first and the second dies.
 9. The die of claim 1,integrated into at least one of a cell phone, hand-held personalcommunication systems (PCS) units, portable data unit, and fixedlocation data unit.
 10. An integrated circuit package comprising: afirst die disposed on a substrate; a second die disposed on thesubstrate; and a bridge die interconnecting the first die to the seconddie, the bridge die comprising conductive through vias coupled toconductive lines on a first side of the bridge die to enable theinterconnecting.
 11. The package of claim 10, in which the bridge die isdisposed at least partially on first sides of the first die and thesecond die.
 12. The package of claim 10, in which the bridge die furthercomprises active circuitry on the first side.
 13. The package of claim10, further comprising a plurality of contact pads on the second side ofthe bridge die contacting corresponding contact pads on first sides ofthe first and second dies.
 14. The package of claim 10, in which atleast one of the first and second die comprise: a flip-chip die havingcircuitry disposed on a second side, the flip-chip die being coupled tothe substrate by ball bonding, solder bump bonding or conductive paste;and flip-chip through vias extending from the first side to the secondside of the flip-chip die; the flip-chip through vias being filled withconductive material to couple conductive lines on the second side to atleast one contact pad on the first side of the flip-chip die.
 15. Thepackage of claim 10, in which at least one of the first and second diecomprise circuitry disposed on the first side of the first and seconddie.
 16. The package of claim 10, further comprising: at least oneadditional die stacked on the bridge die, the at least one additionaldie further comprising at least one of passive, active and interconnectcircuitry.
 17. The package of claim 10, in which the bridge die isfabricated using a process flow that is different from a process flowcorresponding to at least one of the first and the second dies.
 18. Thepackage of claim 10, integrated into at least one of a cell phone,hand-held personal communication systems (PCS) units, and portable dataunit, and fixed location data unit.
 19. An integrated circuit packagecomprising: a first die disposed on a substrate; a second die disposedon the substrate; and means for interconnecting the first die to thesecond die, the interconnecting means comprising conductive through viascoupled to conductive lines on a first side of the interconnecting meansto enable the interconnecting.
 20. The package of claim 19, integratedinto at least one of a cell phone, hand-held personal communicationsystems (PCS) units, and portable data unit, and fixed location dataunit.